A data processing system which utilizes microinstructions conventionally requires appropriate control of the sequencing of the microinstructions which are generated as a result of the decoding of a macroinstruction.
A particular system for providing control of such sequencing operation (a "microsequencing" process) is illustrated in copending U.S. patent application Ser. No. 143,710, filed Apr. 25, 1980 by C. J. Holland et al., refiled as continuation application, Ser. No. 473,560, on Mar. 9, 1983, now issued as U.S. Pat. No. 4,554,627 on Nov. 19, 1985, in which a decoded macroinstruction provides the starting address of a sequence of one or more microinstructions representing a microroutine. The starting address is supplied to a unique microinstruction sequencing unit, in the system described therein, which unit appropriately decodes a selected field of each microinstruction for determining the address of the next successive microinstruction, the address being suitably selected from a plurality of microaddress sources. An exemplary overall configuration in which such a microsequencer is utilized is described in the above-referenced application and such application is, accordingly, incorporated by reference herein.
As described in the aforesaid application, the entire microinstruction set for the system is loaded into a microcontrol store means, e.g., a random access memory (RAM), and the starting address of a particular sequence thereof is supplied from a suitable instruction processor unit which decodes a macroinstruction for such purpose. The microsequencer unit then must determine the next address required for each sequential microinstruction (if any) via appropriate decoding of a "next address control" field of the current microinstruction. An address multiplexer unit is utilized to select the source of the address for the next sequential microinstruction, such microaddress being obtained from one of a number of different sources, e.g., from an incremented micro-program counter unit, from a temporary storage of microaddresses for a particular microcode routine which are stored in a stack RAM unit, from an address which has been accessed from the stack and saved in a previous operation, from an address which is supplied from a source external to the microsequencer unit itself, from an absolute address supplied externally via a dispatch multiplexer, as discussed in the aforesaid Holland et al. application.
In conventional microinstruction sequencing operations, for each microinstruction that could be subject to a trap condition of some nature, a condition must be tested to determine whether such trap condition has occurred before the microroutine is continued. If a trap condition has occurred and that condition is signified by the condition test, the trap condition is then resolved, as by the performance of an appropriate trap-handling microroutine, for example. Thus, the microprogrammer then must include a condition test instruction for each such microinstruction which could be subject to a trap condition so that such condition can be suitably tested before the performance of the microinstruction that is desired. Further, in conventional systems, the entire microroutine is restarted after the trap condition is resolved. In contrast to such conventional techniques, it is further desirable for all microcode routines to be capable of being interrupted (in a manner which frees up the microcode programming operation) so that the microinterrupt capability is, in effect, not visible to the microprogram and no condition test is required for each microinstruction which might be subject to a trap condition and the microroutine is resumed at the point where the trap condition was detected after such appropriate trap-handling microroutine is completed.